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HOME Test and Measurement Analyzers Logic Agilent Logic Analyzer Modules Keysight Technologies (Agilent HP) U4154A For Sale Keysight Technologies (Agilent HP) U4154U

Keysight Technologies (Agilent HP) U4154U

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Description of Keysight Technologies (Agilent HP) U4154U

Categories: Analyzers Logic, Agilent Logic Analyzer Modules

Manufacturer: Keysight Technologies (Agilent HP)

Model: U4154A

Condition: Used

Seller: Liberty Test Equipment, Inc.

Keysight U4154U Upgrade product for U4154A

Product specifications of Keysight Technologies (Agilent HP) U4154U (From Used-Line T&M Specifications)

  • Launch Date Mar-2011
  • Instrument Type Module
  • Max. Channels Number 136
  • Max. State Speed 2.5 GHz
  • Max. Timing Speed 2.5 GHz
  • Memory Depth 256 Ksamples (nominal, TimingZoom)
  • Options Memory depths: 2M, 4 M, 16 M, 32 M, 64 M, 128 M, 200 M
  • Status --

The Agilent U4154A AXIe-based logic analyzer module provides reliable measurements on high-speed digital systems operating up to 4 Gb/s with eye openings as small as 100 ps by 100 mV. 12.5 GHz Timing Zoom with 256K sample memory gives you simultaneous state and high-resolution timing measurements covering a time span of 20 µs. Eye scan provides an overview of signal integrity information on all channels in a matter of minutes. 200 M samples of available memory ensure you capture enough system activity to troubleshoot complex systems.

  • State analysis (synchronous sampling)
    • Data rates up to 4 Gb/s address all DDR memory speeds
    • Automated threshold/sample position setup for accurate measurements on high-speed buses; thresholds are adjustable on a per-channel basis
    • Reliable measurements with eye openings as small as 100 ps by 100 mV
    • Simultaneous eye diagrams on all channels identify problem signals quickly
  • Timing analysis (asynchronous sampling)
    • Up to 200 ps (5 GHz), 400 M sample deep conventional timing analysis (2.5 GHz full-channel / 5 GHz half-channel)
    • 2.5 GHz transitional timing
    • 12.5 GHz (80 ps) TimingZoom with 256 K memory
  • 136 channels per module, combine up to 2 modules for 272 channels on a single time base and trigger recognizer
  • Optional memory depths: 2M, 4 M, 16 M, 32 M, 64 M, 128 M, 200 M
  • Compatible with 90-pin logic analyzer probes (probes ordered separately)
  • Can be combined with 16902B logic analyzer mainframes in a Multiframe configuration
  • 2.5 GHz trigger sequencer enables reliable trigger and capture of DDR3 2133 signals at speed
  • Comprehensive single-ended and differential signal support, adjustable threshold

Specifications:

  • State (synchronous) sampling mode
    • Maximum state data rate: 2.5 Gb/s on 136 channels per U4145A, using either or both edges of clock; 4 Gb/s on 68 channels per U4165A, using both edges of clock
    • Typical maximum state clock frequency: 2.5 GHz
    • Typical minimum state clock frequency: 12.5 MHz - single edge, 6.25 MHz - both edges
    • Typical sample position adjustment resolution: 5 ps
    • Typical minimum data valid window: 100 ps
    • Typical minimum setup time: 50 ps
    • Typical minimum hold time: 50 ps
    • Typical minimum eye height: 100 mV
    • Typical sample position adjustment range: 7 ns
    • Typical minimum state clock pulse width: 200 ps
    • Nominal number of clocks: 1
    • Typical minimum time between active clock edges: 400 ps
    • Typical maximum time between active clock edges: 80 ns
    • Nominal number of clock qualifiers: 4
    • Typical clock qualifier setup time: 100 ps
    • Typical clock qualifier hold time: 100 ps
    • Typical time tag resolution: 80 ps
    • Typical maximum time count between stored states: 66 days
  • Timing (asynchronous) sampling mode
    • Nominal maximum sample rate: 5 GHz in half-channel mode, 2.5 GHz in full-channel mode
    • Nominal minimum sample period: 200 ps in half-channel mode, 400 ps in full-channel mode
    • Number of channels: One U4154A - 68 in half-channel mode, 136 in full-channel mode; Two U4154As - 136 in half-channel mode, 272 in full-channel mode
    • Nominal pod usage: 1 pod from each odd/even pair, user selectable in half-channel mode, all pods in full-channel mode
    • Nominal TimingZoom sampling rate: 12.5 GHz
    • Nominal TimingZoom memory depth: 256 Ksamples
    • Nominal maximum time between transitions: 66 days
    • Typical minimum data pulse width: 1 sample period + 200 ps
  • Triggering
    • Typical maximum trigger sequence speed: 2500 MHz (400 ps)
    • Nominal trigger resources: 16 patterns evaluated as =, !=, >, ≥, <, ≤; 8 double-bounded ranges evaluated as in range, not in range; 4 to 8 burst detectors; 4 edge detectors in timing, 3 in transitional timing; 1 occurrence counter per sequence level; 1 timer; 3 flags; 1 arm in
    • Nominal trigger resource Boolean conditions: Arbitrary Boolean combinations
    • Nominal trigger actions: Goto; Trigger and fill memory; Trigger and Goto; Trigger, send email, and fill memory
    • Timer actions: Start from reset, Stop and reset, Pause, Resume
    • Flag actions: Set, Clear, Pulse set, Pulse clear
    • Nominal maximum trigger sequence levels; 8
    • Nominal trigger sequence level branching: Arbitrary 4-way if/then/else
    • Nominal trigger position: Start, center, end, or user-defined
    • Nominal maximum occurrence counter: 999,999,999
    • Nominal maximum pattern width: 128 bits - single label; 272 bits - AND of multiple labels across two-card set
    • Nominal maximum range width: 64 bits
    • Nominal timer range: 100 ns to 27 hours in timing modes; 200 * state clock period to 27 hours in state mode
    • Nominal timer resolution: 5 ns
    • Nominal timer reset latency: 40 ns in timing modes; 80 * state clock period in state mode

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