The HP 16550A State/Timing Analyzer module is part of a new

generation of general-purpose logic analyzers. The HP 16550A

module is used with the HP 16500B/C mainframe, which is designed

as a stand-alone instrument for use by digital and microprocessor

hardware and software designers. The HP 16500B/C mainframe has

HP-IB and RS-232-C interfaces for hard copy printouts and control by

a host computer.

The HP 16550A State/Timing Analyzer module has 96 data channels,

and six clock/data channels. A second HP 16550A card can be added

to expand the module to 204 data and clock/data channels.

Memory depth is 4 Kbytes in all pod pair groupings, or 8 Kbytes on

just one pod (half channels). All resource terms can be assigned to

either configured analyzer machine.

Measurement data is displayed as data listings or waveforms, and can

be plotted on a chart or compared to a reference image.

The 100-MHz state analyzer has master, slave, and demultiplexed

clocking modes available. Measurement data can be stamped with

either state or time tags. For triggering and data storage, the state

analyzer uses 12 sequence levels with two-way branching, 10 pattern

resource terms, 2 range terms, and 2 timers/counters.

The 500-MHz timing analyzer has conventional, transitional, and glitch

timing modes with variable width, depth, and speed selections.

Sequential triggering uses 10 sequence levels with two-way branching,

10 pattern resource terms, 2 range terms, 2 timers/counters and 2

edge/glitch terms.

Defining a trigger specification is as easy as picking a predefined

macro from a trigger macro library. Trigger macros can be used by

themselves or in combination with each other.