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HOME Test and Measurement Telecom, Datacom BERTs, Error Analyzers Keysight Technologies (Agilent HP) N4903A-G13 For Sale N4903A G13

N4903A G13

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Description of N4903A G13

Categories: Telecom, Datacom, BERTs, Error Analyzers

Manufacturer: Keysight Technologies (Agilent HP)

Model: N4903A-G13

Condition: Used

Seller: BRL Test, Inc.

N4903A-G13 - Keysight / Agilent Pattern Generators

Keysight / Agilent N4903A-G13 Overview

The new Agilent J-BERT N4903A 7 Gb/s and 12.5 Gb/s pattern generator options are cost-efficient digital stimuli, enabling quick and accurate characterization and compliance test of high-speed serial interfaces. Design and test engineers can use the J-BERT pattern generators to inject clean as well as worst-case jittered pattern and clock signals into the device under test. Analysis tools, such as oscilloscopes, built-in error ratios test (BIST), or other analyzers can be used to monitor the behavior of the device under test under ideal and worst-case conditions.

  • Differential outputs for data, clocks and trigger
  • Variable output voltages covering LVDS, ECL, CML
  • Transitions times < 20 ps
  • Clean pulses with jitter < 9 ps pp
  • High precision delay control input to inject jitter from an external source
  • Calibrated and integrated jitter injection (options J10, J20, both retrofitable)
  • Subrate clocks for generating any reference clock
  • Pattern sequencing and 32 Mbit pattern
  • SSC clocks for computer buses (option J11)

Product specifications of N4903A G13 (From Used-Line T&M Specifications)

  • Launch Date Jan-2007
  • See also N4903A-G07
  • Status --

The new Agilent J-BERT N4903A 7 Gb/s and 12.5 Gb/s pattern generator options are cost-efficient digital stimuli, enabling quick and accurate characterization and compliance test of high-speed serial interfaces. Design and test engineers can use the J-BERT pattern generators to inject clean as well as worst-case jittered pattern and clock signals into the device under test. Analysis tools, such as oscilloscopes, built-in error ratios test (BIST), or other analyzers can be used to monitor the behavior of the device under test under ideal and worst-case conditions.

  • Differential outputs for data, clocks and trigger
  • Variable output voltages covering LVDS, ECL, CML
  • Transitions times < 20 ps
  • Clean pulses with jitter < 9 ps pp
  • High precision delay control input to inject jitter from an external source
  • Calibrated and integrated jitter injection (options J10, J20, both retrofitable)
  • Subrate clocks for generating any reference clock
  • Pattern sequencing and 32 Mbit pattern
  • SSC clocks for computer buses (option J11)

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