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HOME Test and Measurement Telecom, Datacom BERTs, Error Analyzers Keysight formerly Agilent T&M 70842B

Keysight formerly Agilent T&M 70842B

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Description of Keysight formerly Agilent T&M 70842B

Categories: Telecom, Datacom, BERTs, Error Analyzers

Manufacturer: Keysight Technologies (Agilent HP)

Model: 70842B

Condition: Used

Keysight (formerly Agilent T&M) 70842B Error Detector

Description

Description

The HP 70842B error detector module complements the pattern generator module. The HP 70842B occupies 418 MMS module slot and has five Input/Output ports, two on the front panel and three on the rear panel. Operating Frequency Range: HP 70842B: 100Mbit/s to 3Gbit/s. Patterns PRBS, zero substitution/variable mark density test patterns, and word test patterns are as specified for pattern generator modules. The Error Detector counts bit errors by comparing the incoming data bit-by-bit with the internally generated reference pattern. All measurements run during the gating periods, with the exception of Delta Error Count and Delta Error Ratio which run continuously. The error analysis measurements are based on CCITT Rec G.821 and derived from the bit error results. Front Panel LEDs for Gating, Clock Loss, Data Loss, Sync Loss, Errors, and HP-IB / MSIB.

Product specifications of Keysight formerly Agilent T&M 70842B (From Used-Line T&M Specifications)

  • Launch Date Jan-2049
  • Alternative N4906A 3.6 Gb/s Bit Error Ratio Tester
  • See also 70841B
  • Status Discontinued by Manufacturer

The HP 70842B is an error detection module that is built into the 71603B error performance analyzer. It complements the 70841B pattern generator module. The 70842B occupies a 4/8 MMS module slot and has five input/output ports, two on the front panel and three on the rear panel.

  • Operating frequency range: 100 Mbit/s to 3 Gbit/s
  • PRBS patterns
    • 231-1, polynomial D31 + D28 +1 = 0, inverted
    • 223-1, polynomial D23 + D18 +1 = 0, inverted
    • 215-1, polynomial D15 + D14 +1 = 0, inverted
    • 210-1, polynomial D10 + D7 +1 = 0, inverted
    • 27-1, polynomial D7 + D6 +1 = 0, inverted
  • Zero substitution/variable mark density test patterns. Zeros can be substituted for data. The ratio of 1s to total bits can be set to 1/8, 1/4, 1/2, 3/4, 7/8
    • 8192 bits, based on 213-1 PRBS
    • 2048 bits, based on 211-1 PRBS
    • 1024 bits, based on 210-1 PRBS
    • 128 bits, based on 27-1 PRBS
  • Word test patterns. Variable length patterns from 1 to 4194304 bits are provided
  • Error measurements: Counts bit errors by comparing the incoming data bit-by-bit with the internally generated reference pattern. All measurement run during the gating periods, with the exception of Delta Error Count and Delta Error Ratio, which run continously. Error measurements are Error Count, Delta Error Count, Error Ratio, Delta Error Ratio, Errored Intervals (second, decisecond, centisecond, millisecond), Error Free Intervals (second, decisecond, centisecond, millisecond), Error Count 0 -> 1, Error Count 1 -> 0, Error Ratio 0 -> 1, Error Ratio 1 -> 0
  • Error analysis measurements are derived from the bit error results: %Unavailability, %Availability, %Errored Seconds, %Severely Errored Seconds, %Degraded Minutes
  • Power-loss seconds: Displayed as the number of seconds the error detector is not able to perform measurements during a gating period due to ac power loss. The gating continues to the end of the selected period following a restoration of power
  • Frequency measurement: The incoming clock frequency is measured and displayed to five significant digits
  • Measurement period
    • Real-time clock: Provides time and date information for event logging. Battery back-up allows clock to continue running when the instrument is switched off or power fails
    • Manual gating period: Controlled by the Run/Stop gating keys. Accumulating results are displayed throughout the measurement and the end of the measurement results are held until a new gating period is started
    • Single gating period: Started by pressing the Run Gating softkey and terminates at the end of the gating period set by the user or when the Stop Gating key is pressed. Accumulating results are displayed throughout the gating period and the end of gating results are held until a new gating period is started
    • Repeat gating period: Similar to Single but when one timed gating period ends, a new identical period starts. This continues until the measurement is terminated by pressing the Stop Gating key. The measurement results displayed during any period can be the final results of the previous period or the accumulated results for the current period. There is no deadtime between consecutive periods
  • Gating period format
    • A time period ranging from 1 second to 99 days, 23 hours, 59 minutes, 59 seconds
    • The time for a number of errors to occur. Number of errors can be 10, 100, or 1000
    • The time for a number of bits to be received. The number of bits can be in the range of 1E7 through 1E15 in decade steps
  • Error output: The rear panel Error Output port produces an NRZ output pulse when errors occur
  • Pattern synchronization: Can be performed automatically or manually. In manual mode, the Sync Start key forces the error detector to attempt synchronization with the received pattern
  • Sync gain/loss criteria: Synchronization is gained when the measured error rate is less than the set sync threshold. Synchronization loss occurs when the measured error rate exceeds the selected sync threshold. Selectable thresholds between 1 x 10-1 and 1 x 10-8 are provided
  • Sync gain times: For most RAM based patterns, synchronization should occur in approximately 2 to 3 seconds. However synchronization times are dependent on pattern length and pattern content, and will increase as pattern length increases. For very long patterns, times could be of a minute or more
  • Error Count Inhibit: An ECI (active high) signal present at the input will inhibit the error counting of errors in the instrument for a multiple of 16 clock periods
  • Trigger Output: Synchronous with the error detector reference pattern
    • The absolute position of the pulse can vary by 15 bits
    • The position of the trigger pulse relative to a pattern generator trigger can vary by a number of pattern lengths for patterns that are not a multiple of 128 bits
  • Results can be logged to most standard HP-IB 80 column printers
  • Front panel LEDs
    • Gating: Measurements in progress
    • Clock Loss: Nominal low clock power at Clock Input
    • Data Loss: No transitions in the last decisecond. Under certain circumstances, this LED will not be illuminated when there is no signal connected to the DATA IN port. With no input, Auto Threshold sets the input 0/1 threshold to the mean of the idle input. Noise is seen as valid transitions around that threshold. The Data Loss indicator is operative when Manual Threshold is selected and the 0/1 threshold level altered from the Auto Threshold mean value
    • Sync Loss: Illuminated in accordance with sync gain/loss criteria as specified
    • Errors: Indicates one or more data errors in the last decisecond
    • HP-IB/MSIB: Six LEDs indicate status

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