Tektronix PED3202

98 Visitors viewed Testwall Ltd ads in the last 30 Days

The PED3000 Programmable Error Detector is an effective multi channel BER for stressed receiver testing of data communications designs.

Models:

• One-channel programmable error detector: PED3201
• Two-channel programmable error detector: PED3202

The Tektronix PED line of high-performance error detectors offers single and two-channel standalone configurations capable of BER measurement at data rates up to 32 Gb/s. The PED products support either PRBS or user-defined data patterns, with simple to use automatic or manual alignment of input clock and data, and pattern synchronization.

The PED3000 Series can be combined with the PPG3000 to provide up to 32 Gb/s BER analysis with multi-channel support for quick identification of crosstalk issues common in multi-lane data communications architectures. For example, with IEEE802.3ba standards test, designers can simulate a 4 x 28G test bench to stress-test their receivers' designs. The 32 Gb/s data rate output with adjustable jitter insertion enables design firms to bring product to market with industry best margin capabilities, improving yields and performance of their end products or chips.

Available with either one or two channels, the PED3000 Series of error detectors enable comprehensive testing of multi-channel standards like 100G Ethernet. The instruments combine excellent sensitivity (<20mV measured at 30 Gb/s) with the industry's widest data range from 32 Mb/s to 32 Gb/s. Error checking functions include PRBS or user-defined patterns, DC-coupled differential data inputs, single-ended clock input and auto align to input pattern.

• Available with 1 or 2 input channels (independent data on each channel)
• PRBS and user defined patterns
• DC coupled differential data inputs (may also be used single ended or AC Coupled)
• Full rate AC coupled clock input (may also be used single ended)
• Auto adjustment or manual adjustment of data to clock phase
• Auto synchronization to input pattern
• Front panel touch screen GUI or USB TMC computer control
• 25 Gb/s testing for 100G Ethernet
• 32 Gb/s DPQPSK testing
• Semiconductor and component testing
• Design validation and production testing

PED3000 characteristics:

• Data Input: Ground-referenced, CML-like input
  • Differential Use Amplitude: 100 mV to 1.0 V
  • Single-Ended Use Amplitude: 100 mV to 0.75 V
  • Input Window Voltage: –0.6 V to +0.2 V
  • Termination Voltage: 0 V
• Clock Input: AC Coupled, full rate
  • Differential Amplitude: 300 mV to 1.0 V
  • Single-Ended Amplitude: 300 mV to 1.0 V
• Clock to Data Phase Adjustment: 100 ps (–50 ps to +50 ps)
• Built-in PRBS Patterns: 2^n–1 where  n = 7, 9, 11, 15, 23, 31
• User-Defined Pattern Depth: 2 Mbit, single bit pattern resolution