Tektronix BSA286C

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The BERTScope™ BSA Series Bit Error Rate Testers provide a new approach to signal integrity measurements of serial data systems. Perform bit error ratio detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope BSA Series lets you easily isolate problematic bit and pattern sequences, then analyze further with seven types of advanced error analysis that deliver unprecedented statistical measurement depth.

• Pattern generation and error analysis, highspeed BER Measurements up to 28.6 Gb/s
• Integrated, calibrated stress generation to address the stressed receiver sensitivity and clock recovery jitter tolerance test requirements for a wide range of standards
  • Sinusoidal jitter to 100 MHz
  • Random jitter
  • Bounded, uncorrelated jitter
  • Sinusoidal interference
  • Spread spectrum clocking
  • PCIe 2.0 & 3.0 receiver testing
  • F/2 jitter generation for 8xFC and 10GBASE-KR testing
  • IEEE802.3ba & 32G fibre channel testing
• Electrical stressed eye testing for
  • PCI Express
  • 10/40/100 Gb Ethernet
  • SFP+/SFI
  • XFP/XFI
  • OIF/CEI
  • Fibre Channel (FC8, FC16, FC32)
  • SATA
  • USB 3.0
  • InfiniBand (SDR, QDR, FDR, EDR)
• Integrated BER correlated eye diagram analysis with pass/fail masks for PCI Express, USB, SATA and other communications standards
• Error location and BER contour analysis on PRBS 31 and other digital signals up to 28.6 GB/sec
• Jitter tolerance compliance template testing with margin testing
• Fast input rise time / high input bandwidth error detector for accurate signal integrity analysis
• Physical layer test suite with mask testing, jitter peak, BER contour, and Q-factor analysis for comprehensive testing with standard or user-defined libraries of jitter tolerance templates
• Integrated eye diagram analysis with BER correlation
• Patented Error Location Analysis™ enables rapid understanding of your BER performance limitations and assesses deterministic versus random errors, performs detailed pattern-dependent error analysis, performs error burst analysis, or error-free interval analysis
• Optional jitter map provides fast jitter decomposition, accurate stress calibration at the DUT input
• Optional digital pre-emphasis processor provides user controlled pre-emphasis on pattern generator supplied data
• Optional clock recovery units provide clock recovery up to 28.6 Gb/s

Characteristics of the BSA286C (Error Detector):

• Clock input frequency range: 1 to 28.6 Gb/s. From 26 to 28.6 Gb/s the input detector operates at half rate (using even or odd bits)
• Clock input configuration: Single ended
• Data and clock interfaces
  • Connector: APC-3.5 Planar Crown®
  • Impedance: 50 Ω
  • Threshold Voltage: –2 to +3.5 V
  • Threshold Presets: LVPECL, LVDS, LVTTL, CML, ECL, SCFL
  • Terminations: Variable, –2 V to +3 V; Presets: +1.5, +1.3, +1, 0, –2 V, AC coupled
  • Max Nondestructable Input: –3 Vpeak, +4 Vpeak, applied to any connector
• Clock/data delay
  • Range up to 1.1 GHz: 30 ns
  • Range above 1.1 GHz: 3 ns
  • Resolution: 100 fs
• Data input:
  • Data rate range: 1 - 28.6 Gb/s
  • Configuration: Differential
  • Format: NRZ
  • Polarity: Normal or Inverted
  • Threshold Alignment: Can auto-align to differential crossing point
  • Maximum input signal swing: 2 Vp-p
  • Intrinsic Transition Time: 16 ps typical, 10/90%, single ended (equivalent to >20 GHz detector bandwidth). Measured at input, ECL levels
  • Hardware patterns: Industry-standard Pseudo-random (PRBS) of the type 2^{n – 1} where n = 7, 11, 15, 20, 23, 31
  • RAM pattern user defined: 128 bits to 128 Mb, 128-bit increments
  • Ram pattern library: Wide variety including SONET/SDH, Fibre Channel based such as k28.5, CJTPAT; 2ⁿ patterns where n = 3, 4, 5, 6, 7, 9; Mark Density patterns for 2ⁿ where n = 7, 9, 23
  • RAM pattern capture: Capture incoming data up to 128 Mb in length. Edit captured data, send to pattern generator, error detector, or both
  • Capture modes: Capture by length—1 to 1,048,576 words, 1-word default, words 128 bit in length; Capture by triggers—Captures when “Detector Start” on rear panel goes high, to maximum allowable length or until input goes low; Capture by length from trigger—Capture by length initiated from “Detector Start” input, to pre-specified length
  • Synchronization: Auto-resync—User-specified number of 128 bit words containing 1 or more errors per word initiates a re-sync attempt; Manual—User initiates re-sync
  • Pattern matching: Grab ‘n’ Go—Error detector captures specified pattern length and compares next instances to find match (Fast method, but susceptible to ignoring logical errors); Shift-to-Sync—Error detector compares incoming pattern with reference RAM pattern, looks for match, if none found shifts pattern by one bit and compares again (Slower but most accurate method)
  • Error Detector Basic Measurements: BER, Bits Received, Re-syncs, Measured Pattern Generator and Error Detector Clock Frequencies
• Error Correlation Marker Input (Error Analysis): Allows an external signal to provide a time-tagged marker to be placed in the error data set
  • Logic Family: LVTTL (<0.5 V Low, >2.5 V High)
  • Threshold: +1.2 V
  • Minimum Pulse Width: 128 clock periods
  • Maximum Repetition Rate: 512 serial clock periods
  • Maximum Frequency: <4000 markers/s recommended
  • Interface: BNC female, >1 kΩ impedance into 0 V
• Blank input: Useful for recirculating loop fiber experiments or during channel training sequences. Causes errors to be ignored when active. Bit count, error count, and BER not counted. No re-sync occurs when counting is re-enabled
  • Logic Family: LVTTL (<0.5 V Low, >2.5 V High)
  • Threshold: +1.2 V
  • Minimum Pulse Width: 128 clock periods
  • Maximum Repetition Rate: 512 serial clock periods
  • Interface: BNC female, >1 kΩ impedance into 0 V
• Error output: Provides a pulse when an error is detected. Useful for triggering an alarm while doing long-term monitoring
  • Minimum Pulse Width: 128 clock periods
  • Transition Time: <500 ps
  • Output Levels: 1000 mV nominal (0 V to 1 V low-high)
  • Interface: SMA female
• Trigger output: Provides a pulse trigger to external test equipment
  • Modes: Divided Clock Mode—Pulses at 1/256th of the clock rate; Pattern Mode—Pulse at a programmable position in the pattern (PRBS), or fixed location (RAM patterns)
  • Minimum Pulse Width: 128 clock periods (Divided Clock Mode); 512 clock periods (Pattern Mode)
  • Transition Time: <500 ps
  • Output Levels: >300 mV amplitude, 650 mV offset
  • Interface: 50 Ω SMA female
• Detector start input (rear panel): Used to trigger the acquisition of incoming data into the Error Detector reference pattern memory. High level starts capture
  • Amplitude: LVTTL (<0.5 V Low, >2.5 V High)
  • Threshold: +1.2 V
  • Minimum Pulse Width: 128 serial clock periods
  • Maximum Repetition Rate: 512 serial clock periods
  • Interface: SMA female, >1 kΩ impedance into 0 V
• Display: TFT touch screen 640 x 480 VGA
• Supported interfaces
  • DVI/VGA display
  • USB 2.0 (6 total, 2 front, 4 rear)
  • 100BASE-T Ethernet LAN
  • IEEE-488 (GPIB)
  • Parallel printer
  • Serial RS-232