Tektronix TLA7SA16

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The TLA7SA00 Series logic protocol analyzer modules provide an innovative approach to PCI Express validation that spans all layers of the protocol from the physical layer to the transaction layer. Feature rich software provides improved information density for viewing statistical summary and protocol analysis using innovative Transaction and Summary Profile windows. Hardware capabilities, including hardware acceleration, OpenEYE, ScopePHY, and FastSYNC, provide fast access to data and help shorten the time it takes to build confidence in the test system.

TLA7SA00 Series Features and Benefits:

• PCI Express Gen1, Gen2, and Gen3 Protocol to Physical Layer Analysis for Link Widths from x1 through x16 with 8 GT/s Acquisition Rate
• OpenEYE Equalization: You can probe anywhere on the bus thanks to OpenEYE Technology with automatic tuning equalization circuitry
• ScopePHY Probing: Quickly gain confidence that your setup is correct and your PCI signal meets probe input requirements by routing any signal directly to a high bandwidth Oscilloscope
• FastSYNC: Guaranteed resynchronization time to be <12 FTS1 (PCIe2) or <4 FTS2 (PCIe3) regardless of the Electrical Idle time for Advanced Power State Management performance
• Data Storage and HW Accelerated Search: Get access to data and execute searches on any pattern in seconds regardless of record length
• Powerful Trigger-state Machine Spans All Layers of the Protocol
  • 8 States
  • 8 Packet Recognizers
  • 4 Symbol Sequence Recognizers
  • 4 Counter/Timers
  • 4 Event Flags
  • Conditional Storage
  • Real-time Filtering
• Summary Profile Window: Provides a data rich statistics based view of all PCI protocol elements
• Transaction Window: Observe and Analyze Link based behavior of protocol elements (transactions, packets, fields, ordered sets)
• MultiBus Correlation: Get full system visibility of multiple busses (DDR, PCIe, QPI, etc) as well as other system level activity through the legacy power of the Logic Analyzer functionality
• Shorten Time to Gain Confidence in the Test System Setup
  • Front-panel LEDs provide Status Information such as Link Speed, Symbol Lock, and Link Activity
  • Auto-configure sets up the Logic Protocol Analyzer System to be Ready for Data Acquisition Quickly
  • FastSYNC Tracks the Link as it Transitions In and Out of ASPM Power States such as L0s, Regardless of Electrical Idle Duration
  • Real-time Statistics Help Observe Link Health and Behavior over Time
• Deepest 8 GB Memory/Module (16 GB memory, x16 link width) in the Industry Increases the Chances of Capturing an Error and the Fault that Caused the Error

TLA7SA16 Characteristics: 16 Differential Inputs, x8 Logic Protocol Analyzer module, 8 GT/s acquisition, 8 GB physical memory

• Acquisition Rate with Frequency Margin
  • 8 GT/s (+5% to -10%)
  • 5 GT/s (±10%)
  • 2.5 GT/s (±10%)
• Number of Lanes: 16 differential inputs, x8
• Record Length: 160M Symbols per differential input, 8 GB physical memory total (16 GB physical memory for a x16 configuration)
• Time Stamp Range: 292 hours
• Time Stamp: 50 bits at 936 ps resolution
• Clocking/Acquisition Modes TLA module without SSC (Spread Spectrum Clocking), External Reference Clock (100 MHz ±10%) with or without SSC
• External reference clock frequency tolerance: ±300 ppm
• Number of Mainframe Instrument Slots Required per TLA Series Module: 2
• Filter Characteristics
  • Ordered Sets: TS1, TS2, SKP, EIOS, FTS, EIEOS, SDS
  • DLLPs: Ack, Nak, PM, Vendor Specific, FC1, FC2, UpdateFC
  • TLPs: MRd, MRdL, MWr, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CPlLk, CPlDLk, FetchAdd, Swap, CAS, LPrfx, EPrfx
• Trigger Characteristics
  • Independent Trigger States: 8
  • Trigger Sequencer Rate: Operates at symbol rate time (Gen1, Gen2, Gen3)
  • Maximum Independent If/Then Clauses per State: 8
  • Maximum Number of Events per If/Then Clause: 8
  • Maximum Number of Actions per If/Then Clause: 8
  • Maximum Number of Event Counters per State: 2
  • Event Counter Range: 31 bit
  • Number of TLP Packet Recognizers per Link Direction: 4
  • Number of DLLP Packet Recognizers per Link Direction: 4
  • Number of Sequence Recognizers: 4
  • Number of Symbols per Sequence Recognizer: 16
  • Number of Link Event Recognizers: 4
  • Number of Global Counters/Timers: 4
  • Trigger Event Types: Anything, TLP, DLLP, Sequence, Link Event, Counter, Timer
  • Trigger Action Types: Trigger, Trigger All Modules, Wait for System Trigger, Goto, Increment Counter, Decrement Counter, Reset Counter, Start Timer, Reset Timer, Reset and Start Timer, Stop Timer, Reset and Stop Timer, Set Signal Out, Clear Signal Out, Arm Module, Start Storage, Stop Storage, Do Nothing
  • Counter/Timer Range: 48 bit (~5 days with 3.6 ns resolution)
  • Counter/Timer Test Latency: 68 ns
  • Storage Control (Data qualification): By state (start/stop)